/*!
    \file    change log.txt
    \brief   change log for GD32A50x demo

    \version 2025-02-20, V1.5.0, demo for GD32A50x
*/

/*
    Copyright (c) 2025, GigaDevice Semiconductor Inc.

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are permitted provided that the following conditions are met:

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*/

******************* V1.5.0 2024-12-31 ************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
..\GD32A50x_Demo_Suites\GD32A50x_Firmware_Library
fix reason:
Updated the firmware library to the latest version V1.4.0.

******************* V1.4.0: 2024-08-02 ************************************************************************************
______________________Common______________________________________________________________________________________________
Fix file:
gd32a50x_it.c in each demo's 
fix reason:
SRAM ECC single-bit errors will not trigger an NMI exception.
V1.3.0:
void NMI_Handler(void)
{
    if(SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_SRAMECCMERR)) {
        SRAM_ECC_ERROR_HANDLE("SRAM multi-bits non-correction ECC error\r\n");
    }else if(SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_SRAMECCSERR)) {
        SRAM_ECC_ERROR_HANDLE("SRAM single bit correction ECC error\r\n");
    }else if(SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_FLASHECCERR)){
        FLASH_ECC_ERROR_HANDLE("FLASH ECC error\r\n");
    }else{
        /* if NMI exception occurs, go to infinite loop */
        /* HXTAL clock monitor NMI error or NMI pin error */
        while(1) {
        }
    }
}
V1.4.0:
void NMI_Handler(void)
{
    if(SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_SRAMECCMERR)) {
        SRAM_ECC_ERROR_HANDLE("SRAM multi-bits non-correction ECC error\r\n");
    } else if(SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_FLASHECCERR)) {
        FLASH_ECC_ERROR_HANDLE("FLASH ECC error\r\n");
    } else {
        /* if NMI exception occurs, go to infinite loop */
        /* HXTAL clock monitor NMI error or NMI pin error */
        while(1) {
        }
    }
}

Fix file:
gd32a50x_it.c in each demo's 
fix reason:
Add FPU and SRAMECC single-bit error interrupt handlers, with these interrupts being enabled by default to prevent unexpected 
interrupts caused by application code and to provide user notifications.
V1.3.0:
none
V1.4.0:
void FPU_IRQHandler(void)
{
    /* if FPU error occurs, go to infinite loop */
    while(1) {
    }
}

void SRAMC_ECCSE_IRQHandler(void)
{
    if(SET == syscfg_interrupt_flag_get(SYSCFG_INT_FLAG_SRAMECCSERR)) {
        SRAM_ECC_ERROR_HANDLE("SRAM single bit ECC error\r\n");
    }
}

Fix file:
gd32a50x_it.h
fix reason:
Add the declaration of the SRAMC_ECCSE_IRQHandler and FPU_IRQHandler function. 
V1.3.0:
none
V1.4.0:
/* this function handles SRAM and Flash single bit ECC non-correction exception */
void SRAMC_ECCSE_IRQHandler(void);
/* this function handles FPU exception */
void FPU_IRQHandler(void);

Fix file:
All functions in the file that involve the use of a serial port.
fix reason:
Modify the serial port redirection function to adapt to the Embedded Builder IDE.
V1.3.0:
/* retarget the C library printf function to the USART */
int fputc(int ch, FILE *f)
{
    usart_data_transmit(EVAL_COM0, (uint8_t)ch);
    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
    return ch;
}
V1.4.0:
#ifdef GD_ECLIPSE_GCC
/* retarget the C library printf function to the USART, in Eclipse GCC environment */
int __io_putchar(int ch)
{
    usart_data_transmit(EVAL_COM0, (uint8_t) ch );
    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
    return ch;
}
#else
/* retarget the C library printf function to the USART */
int fputc(int ch, FILE *f)
{
    usart_data_transmit(EVAL_COM0, (uint8_t)ch);
    while(RESET == usart_flag_get(EVAL_COM0, USART_FLAG_TBE));
    return ch;
}
#endif /* GD_ECLIPSE_GCC */
__________________________________________________________________________________________________________________________

______________________Module CAN__________________________________________________________________________________________
Fix file:
../Projects/15_CAN_Network/main.c
fix reason:
When the CAN TX pin is not pulled up with a resistor between it and the transceiver, prevent the CAN TX pin from being pulled down.
V1.3.0:
gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13);
gpio_mode_set(GPIOD, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_6); 
V1.4.0:
gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_13);
gpio_mode_set(GPIOD, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_6); 

Fix file:
../Projects/15_CAN_Network/main.c
fix reason:
During the transmission process, data is moved from the mailbox to the internal buffer area after being written, and then sent to the bus from the internal buffer area. When the bus load is too high and there are no restrictions on the sending operation, directly writing to the transmission mailbox again before the move-out operation is completed can cause the state machine to incorrectly unlock the receive mailbox.
V1.3.0:
none
V1.4.0:
if((RESET == can_tx_state) || (SET == can_flag_get(CAN1, CAN_FLAG_MB1))){
} 
__________________________________________________________________________________________________________________________
